Integrated circuits can be formed as semiconductor devices on a die of a wafer. The die can have large numbers and types of devices formed therein, such as memory, logic circuits, amplifiers, inverters, transistors, and the like. The organization of these devices on a die is referred to as a layout or device layout.
The device layout for a given die can be organized in cells, which comprise individual units for devices. For example, a cell can comprise circuits such as a particular logic device, an amplifier, and the like or individual or groups of components such as transistors, inverters, capacitors, and the like. Standardized cell designs, also referred to as library cells, can be employed in the layout process. Additionally, blank or filler cells can also be employed to mitigate dishing and/or other problems during fabrication. Layouts can be designed by identifying or selecting cells for a particular die and arranging the cells on the die.
A continuing trend for semiconductor device fabrication and integrated circuit fabrication is to reduce device sizes and dimensions. So doing increases the density of devices on devices and leads to cost savings and performance enhancement. However, contact resistance and/or contact capacitance tend to increase with every reduction in scale, also referred to as technology node. Contact resistance and/or contact capacitance have a significant impact upon circuit performance. Thus, continued scaling of devices can result in decreased device performance.
Conventional layout design typically only considers which cells to include for a given design layout and is not concerned with contact resistance and/or contact capacitance. Thus, continued scaling of devices can result in integrated circuits with lowered performance.